V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes. In prior art FeRAM memories, in order to simplify process development, a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.
FIG. 1 shows a top view of a conventional layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 110. There is a huge space between the V0-mask 101 and the masks 103, 105, 107.
FIG. 2 shows a cross-sectional view of the conventional layout of an FeRAM memory chip 200. A cover layer 201 (solid line) is over a BE-mask 107 (the cover layer can be Al2O3, for example). The TE 207 and a bottom electrode BE 209 sandwich a PZT ferroelectric layer 211 forming a ferroelectric capacitor 213 of a capacitor stack 223 of the FeRAM memory chip 200. An encapsulation layer 216 (solid line) is deposited onto the TE 207 prior to depositing the TE-mask 105. An encapsulation layer 215 (solid line) covers the ferroelectric capacitor 213. The cover layer 201 and encapsulation layers 215, 216 help protect the ferroelectric capacitor 213 from damage.
A TW-contact 205 extends through the cover layer 201, TE-mask 105, and the encapsulation layers 215, 216, to provide an electrical connection to a top electrode TE 207.
A CS-contact 223 provides a contact to the source/drain of a CMOS device. A V0-contact 221 passes though a dielectric covering 222 and connects electrically to the CS-contact 223. As can be seen, there is a huge space between the V0-contact 221 and a capacitor stack contact 223, making the memory chip 200 large. In the prior art, despite the cover and encapsulation layers, this huge space has been necessary to prevent short circuits and capacitor damage.
It would be desirable to reduce the size of the memory cell and overall FeRAM chip without the resulting short circuits or capacitor damage.